As the complementary metal oxide semiconductor (CMOS) devices scale down, it becomes more critical to control stress, surface roughness, and defects in metal silicide layers, due to the increased impact of these factors on CMOS device performance and product yield.
Meanwhile, carrier (i.e., either electron or hole) mobility reduces with the sizes of the CMOS devices, which results in unsatisfactory device performance. The reduction in carrier mobility is caused by increased dopant concentration in the channel regions of the scaled-down CMOS devices. However, higher dopant concentration is necessary for reducing short channel effects in the scaled-down CMOS devices.
There is therefore a need for improving the carrier mobility in the channel regions of CMOS devices without reducing dopant concentration thereat.
There is further a need for reducing defects, sheet resistance, and surface roughness of the metal silicide layers contained by the CMOS devices.